A number of devices, for instance mobile applications such as portable devices, require the use of a frequency synthesizer for operation. One such frequency synthesizer includes a digital-to-phase converter (DPC) having a delay-locked loop (DLL). FIG. 1 illustrates a block diagram of a prior art DPC 10 configuration for generating an output signal 82 at a desired frequency Fout. DPC 10 comprises a fixed frequency source 20 for generating a clock signal 22 having a frequency of Fclk. DPC 10 further comprises: a delay-locked loop 30 that includes a primary delay line 32 having N number of adjustable delay elements D1 through DN and a phase detector 40, a charge pump 50 and a low pass filter 60, which make up a stabilization circuit for DLL 30; a plurality of cascaded delay lines 70 (e.g., delay lines DL0 through DL(N−1) that each include a plurality of delay elements (not shown); a selection circuit 80 that may be, for instance, a multiplexer (also referred to herein as a “MUX”); and a digital control device 90 such as, for instance, a digital-to-phase sequencer (DPS).
In operation, delay line 32 receives the clock signal 22 into an input and then generates a set of time delayed (or phase-shifted) clock signals at a plurality of outputs. The time delays are generated by delay elements D1 through DN, which are connected in cascade and which may be, for instance, inverter gates, transmission line gates, and the like, depending upon a desired DPC implementation. Moreover, an overall time delay between a signal at a first point on the delay line, which is typically an input of the first delay element D1, and a signal at a second point on the delay line, which is typically the output of the Nth delay element DN, is controlled by a control signal, e.g., a bias voltage Vtune, input into delay line 32. This overall delay may be, for instance, a wavelength (i.e., 360 degrees) which is one period of clock signal 22, a half wavelength (i.e., 180 degrees) which is one half period of clock signal 22, or whatever delay is required for a particular application. Ideally, each delay element will replicate the input waveform, with a time delay, at the delay element output that is equal to the total delay from the input of delay element D1 through the output of delay element DN divided by the total number of delay elements (i.e., N).
Each delay element D1-D(N−1) has an output tap T1-T(N−1), respectively, which is connected to an input of a respective delay line DL of the plurality of delay lines 70. In addition, a tap T0 is connected between the input of the delay element D1 and an input of delay line DL0. Each delay element D1-D(N−1) delays the propagation of the clock signal 22 and outputs on its corresponding output tap T1-T(N−1), respectively, a corresponding phase-shifted clock signal. Accordingly, the number N−1 of phase-shifted clock signals output by delay elements D1-D(N−1) are supplied via output taps T1-T(N−1) to the inputs of cascaded delay lines DL1 through DL(N−1) along with the clock signal 22 output (i.e., a zero time delay) on tap T0.
To ensure stability during operation, DPC 10 includes phase detector 40 that is typically connected to receive the clock signal 22 from source 20 and a phase-shifted clock signal from delay line 32, which in this instance is the signal at the output of delay element DN. Phase detector 40 compares the phase difference between the clock signal 22 and the phase-shifted clock signal to a predetermined desired phase shift and outputs to the charge pump an error signal that is a function of the result of this comparison.
The charge pump 50 deposits a corresponding charge on the low pass filter 60, which in turn converts the error signal into a DLL tuning signal that is supplied to delay line 32 to adjust the bias voltage Vtune in a manner that maintains the phase relationship between the phase-shifted clock signal and the clock signal 22 during operation of DLL 30, i.e., until the total delay through the delay line 32 is the desired delay. Once DLL 30 has stabilized, MUX 80 operates in a conventional way under the control of DPS 90 to connect, one at a time, a sequence of phase-shifted clock signals to the output of MUX 80 to provide an output signal 82 at the desired output frequency Fout.
A high speed accumulator is typically used as the core of DPS 90 whose digital input 92 is used to program the desired frequency and whose digital output 94 is used by MUX 80 to select the appropriate delay path for the desired output edge of the synthesized output clock 82. The DPS 10 thus provides a coarse delay select and a fine delay select. The coarse delay is provided by the delay elements in the primary delay line 32, and the fine delay is provided by the array of preferably passive delay lines 70 that are cascaded after the outputs of each of the coarse delay elements. The end result of this implementation is the generation of a multiplicity of clock edges that are delayed in time over ideally 1 period of the input reference clock.
These edge times are said to be quantized based on the cumulative delay of each delay element in a delay path. By properly decoding the DPS output, it is possible to synthesize a clock with a different frequency than the input reference clock. It is known that the spurious performance of DPC 10 is inversely related to the number of delay elements included in DPC 10. Thus, to obtain the spurious requirements for certain applications, thousands of delay elements or quantization steps would be required. However, this presents implementation problems.
For example, depending on the number of delay elements required, it may not be possible to integrate all of the delay elements onto a single integrated circuit. Moreover, if an active delay cell approach were used, this would negatively impact overall current drain. Nonetheless, if a passive delay cell (e.g. a transmission line) approach were used, the performance of the DPC would be highly susceptible to process variation (which could negatively impact monotonicity) due to mismatch or loading and result in a loss of performance. In addition, the passive delay element approach is not portable to future IC technologies. This is because a frequency synthesizer designed for a specific process will have its components designed for that process in order to maximize the performance of the synthesizer. This would likely necessitate the frequency synthesizer being redesigned for each additional alternative process to accordingly maximize its performance for those processes.
Thus, there exists a need for a method and apparatus for frequency synthesis that uses a significantly fewer number of delay elements to achieve comparable accuracy and spurious performance to frequency synthesizers known in the art.